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| - 1 - august 08, 2012 | data sheet | rev 3.3 1 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 78 80 82 84 86 88 90 92 94 96 98 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) efficiency (%) 1.2vout 3.3vout 12vin,internal bias,frequency 600khz features ? single 5v to 2 1v application ? wide input voltage range from 1.0v to 2 1v with external vcc ? output voltage range: 0.5v to 0.86* vin ? enhanced line/load regulation with feed - forward ? programmable switching frequency up to 1.5mhz ? internal digital soft - start/ soft - stop ? enable input with voltage monitoring capability ? therma l l y compensated current limit with robust hiccup mode over current protection ? smart internal ldo to impro ve light load and full load efficiency ? external synchronization with smooth clocking ? enhanced pre - bias start - u p ? precision reference voltage (0.5v+/ - 0.5%) with m argining capability ? v p for tracking applications (source/sink capability +/ - 6a ) ? integrated mosfet drivers and bootstrap d iode ? thermal shut down ? programmable power good output with tracking capability ? monotonic start - up ? operating temp: - 40 o c < tj < 125 o c ? small size : 4mm x 5mm p qfn ? lead - free, halogen - free and rohs compliant basic application boot vcc/ ldo_out fb comp gnd pgnd sw vo pgood pgood rt/sync 6.8v - 3 - august 08, 2012 | data sheet | rev 3.3 3 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 block diagram gate drive logic + - soft start + control logic fault vcc vp fb rt/sync b oot sw pgnd pv in enable e / a vcc vcc / ldo _ out over current protection fault control uvcc uven fault fault pg ood oc thermal shut down tsd hdin c omp ldin intl _ ss uvcc uven vref + hdrv ldrv vin + - v ldo _ r ef ldo v ref ssok 0.5v fb vref vp por por por por uvcc por gnd zero crossing comparator dcm dcm vsns oc s_ctrl over voltage protection ov vref ov ov vin rff 0.15v figure 3 : ir3898 simplified block diagram - 4 - august 08, 2012 | data sheet | rev 3.3 4 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 pin descriptions pin # pin name pin description 1 f b inverting input to the error amplifier. this pin is connected to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 v ref internal reference voltage, it can be used for margining operation also. in normal and sequencing mode operation, vref is left floating. a 1nf ceramic capacitor is recommended between this pin and gnd. in tracking mode operation, vref should be tied to g nd. 3 c omp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb to provide loop compensation. 4 g nd signal ground for internal reference and control circuitry. 5 rt /s ync multi - function pin to set switching frequency. use an external resistor from this pin to gnd to set the free - running switching frequency. or use an external clock signal to connect to this pin through a diode, the devices switching frequency is synchronized with the external c lock. 6 s_c trl soft start/stop control. a high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. pull this pin high if this function is not used. 7 pg ood power good status pin. output is open drain. connect a pull up resistor (49.9k) from this pin to the voltage lower than or equal to the vcc. 8 v sns sense pin for over - voltage protection and pgood. it is optional to tie this pin to fb pin directly instead of using a resistor divider from vout. 9 v in input voltage for internal ldo. a 1.0f capacitor should be connected between this pin and pgnd. if external supply is connected to vcc/ldo_out pin, this pin should be shorted to vcc/ldo_out pin. 10 vcc /ldo_o ut input bias for external vcc voltage/ output of internal ldo. place a minimum 2.2f cap from this pin to pgnd. 11 pg nd power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the systems power ground plane. 12 sw switch node. this pin is connected to the output inductor. 13 pv in input voltage for power stage. 14 b oot supply voltage for high side driver, a 100nf capacitor should be connected between this pin and sw pin. 15 enable enable pin to turn on and off the device, if this pin is connected to pvin pin through a resistor divider, input voltage uvlo can be implemented. 16 vp input to error amplifier for tracking purposes. in the normal operation, it is left floating and no external capacitor is required . in the sequencing or the tracking mode operation, an external signal can be applied as the reference. 17 g nd signal ground for internal reference and control circuitry. - 5 - august 08, 2012 | data sheet | rev 3.3 5 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 absolute maximum rat ings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pv in, vin - 0.3v to 25v vcc /ldo_out - 0.3v to 8v (note 2) b oot - 0.3v to 33v sw - 0.3v to 25v (dc), - 4v to 25v (ac, 100ns) b oot to sw - 0.3v to vcc + 0.3v (note 1) s_c trl , pg ood - 0.3v to vcc + 0.3v (note 1) other input/output pins - 0.3v to +3.9v pg nd to g nd - 0.3v to +0.3v storage temperature range - 55c to 150c junction temperature range - 40c to 150c (note 2) esd classification (hbm jesd22 - a114) 2k v moisture sensitivity level jedec level 2@260c note 1: must not exceed 8v note 2: vcc must not exceed 7.5v for junction temperature between - 10c and - 40c - 6 - august 08, 2012 | data sheet | rev 3.3 6 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 electrical specifications recommended operatin g conditions for rel iable operation with margin symbol min max units input voltage range * pv in 1.0 21 v input voltage range ** v in 6.8 21 supply voltage range *** v cc 4.5 7.5 supply voltage range boot to sw 4.5 7.5 output voltage range v o 0.5 0.86 x vin output current range i o 0 6 a switching frequency f s 300 1500 khz operating junction temperature t j - 40 125 c *maximum sw node voltage should not exceed 25v. * *for internal ly biased single rail operation . *** vcc/ldo_o ut can be connected to an external regulated supply. if so, the vin pin should be connected to vcc/ldo_o ut pin. e lectrical characteri stics unless otherwise specified, these specifications apply over, 6.8v < v in = pvin < 2 1v, vref = 0.5v in 0c < t j < 125c . typical values are specified at t a = 25c. parameter symbol conditions min typ max unit power stage power losses p loss v in = 12v, v o = 1.2v, i o = 6a, fs = 600khz, l = 1uh, vcc = 6.4v, note 4 0.85 w top switch r ds(on)_top v boot - vsw= 6.4v, i o = 6a , t j =25c 1 7.5 22.5 m? bottom switch r ds(on)_bot vcc = 6.4v, i o = 6a , t j =25c 11. 4 14.8 bootstrap diode forward voltage i(boot) = 10ma 180 260 470 mv sw leakage current i sw sw = 0v, enable = 0v 1 a sw = 0v, enable = high, vp = 0v dead band time t db note 4 5 10 30 ns supply current vin supply current (standby) i in(standby) en = low, no switching 100 a vin supply current (dynamic) i in(dyn) en = high, fs = 600khz, vin = pvin = 21v 11 15 m a v cc/ ldo _ out output voltage v cc vin(min) = 6.8v, i cc = 0 - 30ma, cload = 2.2uf, dcm = 0 6.0 6.4 6.7 v vin(min) = 6.8v, i cc = 0 - 30ma, cload = 2.2uf, dcm = 1 4.0 4.4 4.8 ldo drop out voltage v cc_drop i cc =30ma,cload=2.2uf 0.7 v short circuit current ishort 70 ma - 7 - august 08, 2012 | data sheet | rev 3.3 7 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 parameter symbol conditions min typ max unit zero - crossing comparator delay tdly_zc note 4 256/fs s zero - crossing comparator offset vos_zc note 4 - 4 0 4 mv oscillator rt voltage vrt 1.0 v frequency range f s rt = 80.6k 270 300 330 khz rt = 39.2k 540 600 660 rt = 15.0k 1350 1500 1650 ramp amplitude vramp vin = 7.0 v, vin slew rate max = 1v/s, note 4 1.0 5 vp - p vin = 12v, vin slew rate max = 1v/s, note 4 1.80 vin = 16v, vin slew rate max = 1v/s, note 4 2.39 vin =vcc=5v, for external vcc operation, note 4 0.75 ramp offset ramp(os) note 4 0.16 v min pulse width tmin(ctrl) note 4 60 ns max duty cycle dmax fs = 300khz, pvin = vin = 12v 86 % fixed off time toff note 4 200 250 ns sync frequency range fsync 270 1650 khz sync pulse duration tsync 100 200 ns sync level threshold high 3 v low 0.6 error amplifier input offset voltage vos_vref vfb C vref, vref = 0.5v - 1.5 +1.5 % vos_vp vfb C vp, vp = 0.5v - 1.5 +1.5 input bias current ifb(e/a) - 1 +1 a input bias current ivp(e/a) 0 +4 sink current isink(e/a) 0.4 0.85 1.2 ma source current isource(e/a) 4 7.5 11 ma slew rate sr note 4 7 12 20 v/s gain - bandwidth product gbwp note 4 20 30 40 mhz dc gain gain note 4 100 110 120 db maximum output voltage vmax(e/a) 1.7 2.0 2.3 v minimum output voltage vmin(e/a) 100 mv common mode input voltage 0 1.2 v reference voltage feedback voltage vfb vref and vp pin floating 0.5 v accuracy 0 c < tj < + 70 c - 0.5 +0.5 % - 8 - august 08, 2012 | data sheet | rev 3.3 8 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 parameter symbol conditions min typ max unit - 40c < tj < + 125c - 1.0 +1.0 % vref margining voltage vref_marg 0.4 1.2 v sink current isink_vref vref = 0.6v 12.7 16.0 19.3 a source current isrc_vref vref = 0.4v 12.7 16.0 19.3 vref comparator threshold vref_disable vref pin connected externally 0.15 v vref_enable 0.4 soft start/stop soft start ramp rate ramp(ss_start) 0.16 0.2 0.24 mv/s soft st op ramp rate ramp(ss_stop) - 0.24 - 0.2 - 0.16 s_ctrl threshold high 2.4 v low 0.6 power good pgood turn on threshold vpg(on) vsns rising, 0.4v < vref < 1.2v 85 90 95 % vref vsns rising, vref < 0.1v 85 90 95 % vp pgood lower turn off threshold vpg(lower) vsns falling, 0.4v < vref < 1.2v 80 85 90 % vref vsns falling, vref < 0.1v 80 85 90 % vp pgood turn on delay vpg(on)_dly vsns rising ,see vpg(on) 1.28 ms pgood upper turn off threshold vpg(upper) vsns rising, 0.4v < vref < 1.2v 115 120 125 % vref vsns rising, vref < 0.1v 115 120 125 % vp pgood comparator delay vpg(comp)_ dly vsns < vpg(lower) or vsns > vpg(upper) 1 2 3.5 s pgood voltage low pg(voltage) i pgood = - 5ma 0.5 v tracker comparator upper threshold vpg(tracker_ upper) vp rising, vref < 0.1v 0.4 v tracker comparator lower threshold vpg(tracker_ lower) vp falling, vref < 0.1v 0.3 tracker comparator delay tdelay(tracker) vp rising, vref < 0.1v ,see vpg(tracker_upper) 1.28 ms under - voltage lockout vcc - start threshold v cc _uvlo_start vcc rising trip level 4.0 4.2 4.4 v vcc - stop threshold v cc _uvlo_stop vcc falling trip level 3.7 3.9 4.1 enable - start - threshold enable_uvlo_start supply ramping up 1.14 1.2 1.26 v enable - stop - threshold enable_uvlo_stop supply ramping down 0.95 1 1.0 5 enable leakage current ien enable = 3.3v 1 a over - voltage protection ovp trip threshold ovp_vth vsns rising, 0.45v < vref < 1.2v 115 120 125 % vref vsns rising, vref < 0.1v 115 120 125 % vp - 9 - august 08, 2012 | data sheet | rev 3.3 9 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 parameter symbol conditions min typ max unit ovp comparator delay ovp_tdly 1 2 3.5 s over - current protection current limit i l imit tj = 2 5c, vcc = 6.4v 7.5 9.0 10.5 a hiccup blanking time tblk_hiccup note 4 20.48 ms over - temperature protection thermal shutdown threshold ttsd note 4 145 c hysteresis ttsd_hys note 4 20 note 3: cold temperature performance is guaranteed via correlation using statistical quality control. not tested in production. note 4: guaranteed by design but not tested in production . - 10 - august 08, 2012 | data sheet | rev 3.3 10 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 78 80 82 84 86 88 90 92 94 96 98 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) efficiency (%) 1.0v 1.2v 1.8v 3.3v 5.0v 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) power dissipation(w) 1.0v 1.2v 1.8v 3.3v 5.0v typical efficiency a nd power loss curves p v in = 12v, v cc = internal ldo (4.4v/6.4v), io = 0a - 6a , fs = 6 00 k hz, room temperature, no air flow . note that the efficiency and power loss curves include the losses of ir3898, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) lout (h) p/n dcr (m?) 1.0 0.82 spm6550t - r82m (tdk) 4.2 1.2 1.0 spm6550t - 1r0m (tdk) 4.7 1.8 1.0 spm6550t - 1r0m (tdk) 4.7 3.3 2.2 7443340220(wurth elektronik) 4.4 5 2.2 7443340220(wurth elektronik) 4.4 - 11 - august 08, 2012 | data sheet | rev 3.3 11 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 83 85 87 89 91 93 95 97 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) efficiency (%) 1.0v 1.2v 1.8v 3.3v 5.0v 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) power dissiation(w) 1.0v 1.2v 1.8v 3.3v 5.0v typical efficiency a nd power loss curves p v in = 12v, v cc = external 5v, io = 0a - 6a , fs = 6 00 k hz, room temperature, no air flow . note that the efficiency and power loss curves include the losses of ir3898, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) lout (h) p/n dcr (m?) 1.0 0.82 spm6550t - r82m (tdk) 4.2 1.2 1.0 spm6550t - 1r0m (tdk) 4.7 1.8 1.0 spm6550t - 1r0m (tdk) 4.7 3.3 2.2 7443340220(wurth elektronik) 4.4 5 2.2 7443340220(wurth elektronik) 4.4 - 12 - august 08, 2012 | data sheet | rev 3.3 12 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 83 85 87 89 91 93 95 97 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) efficiency (%) 1.0v 1.2v 1.8v 3.3v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 load current (a) power dissipation(w) 1.0v 1.2v 1.8v 3.3v typical efficiency a nd power loss curves p v in = 5.0 v, v cc = 5.0v, io = 0a - 6a , fs = 600 k hz, room temperature, no air flow . note that the efficiency and power loss curves include the losses of ir3898, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) lout (h) p/n dcr (m?) 1.0 0.68 pcmb065t - r68ms (cyntec) 3.9 1.2 0.82 spm6550t - r82m(tdk) 4.2 1.8 0.82 spm6550t - r82m(tdk) 4.7 3.3 1.0 spm6550t - 1r0m(tdk) 4.7 - 13 - august 08, 2012 | data sheet | rev 3.3 13 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 6 6.25 6.5 6.75 7 7.25 7.5 25 30 35 40 45 50 55 60 65 70 75 80 85 tamb iout(a) 0 lfm 200 lfm lout -1uh, 4. 7 m ( tdk spm 6550 t -1r 0) 5.5 5.75 6 6.25 6.5 6.75 7 7.25 25 30 35 40 45 50 55 60 65 70 75 80 85 tamb iout(a) 0 lfm 200 lfm lout -1. 5uh, 6. 7m ( cyntec pcmb 065 t -1r 5ms ) thermal derating cur ves measurement i s done on irdc3898 evaluation board , a 4 - layer board with 2 oz copper , fr4 material, size 2.23"x2" p vin = 12v, vout = 1.2v, vcc = internal ldo (6.4v), fs = 600 khz p v in = 12 v, vout = 3.3v, v cc = internal ldo (6.4v), fs = 6 00 khz note: international rectifier corporation specifies current rating of supirbuck devices conservatively. the c ontinuous current l oad c apability might be higher than the rating of the device if input voltage is 12v typical and switching frequency is below 750 khz . the above derating curves are generated at 12v input, 600khz with 0 - 200lfm air flow and ambient temperature up to 85c.detailed thermal derating information can be found in the application note an - 1174 ?thermal derating of dc dc convertors using ir3899/98/97?. however, the maxim um current is limited by the internal current limit and designers need to consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at steady state condition. - 14 - august 08, 2012 | data sheet | rev 3.3 14 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 rdson of mosfets over temperature at v cc =6.4v rdson of mosfets over temperature at v cc= 5.0v - 15 - august 08, 2012 | data sheet | rev 3.3 15 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 t ypi cal operating charac teristics ( - 40c to + 125c) - 16 - august 08, 2012 | data sheet | rev 3.3 16 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 t ypical operating characteristics ( - 40c to + 125c) note: see over current protection section note: see over current protection section - 17 - august 08, 2012 | data sheet | rev 3.3 17 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 theory of operation description the ir 3898 uses a pwm voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the switching frequency is programmable from 300 k hz to 1.5mhz and provides the cap ability of optimizing the design in terms of size and performance. ir 3898 provides precisely regulated output voltage programmed via two external resistors from 0.5v to 0.86* vin . the ir 3898 operates with an internal bias supply (ldo) which is connected to the vcc/ldo_out pin. this allows operation with single supply. the bias voltage is variable according to load condition. if the output load current is less than half of the peak - to- peak inductor current, a lower bias voltage, 4.4v, is used as the internal gate drive voltage; otherwise, a higher voltage, 6.4v, is used. this feature helps the converter to reduce power losses. the device can also be operated with an external supply from 4.5 to 7.5v, allowing an extended operating input voltage (pvin) range fr om 1.0v to 16v. for using the internal ldo supply, the vin pin should be connected to pvin pin. if an external supply is used, it should be connected to vcc/ldo_o ut pin and the vin pin should be shorted to vcc/ldo_o ut pin. the device utilizes the on - resist ance of the low side mosfet (sync fet) for over current protection . this method enhances the converters efficiency and reduces cost by eliminating the need for external current sense resistor. ir 3898 includes two low r ds(on) mosfets using irs hexfet tech nology. these are specifically designed for high efficiency applications. under - voltage lockout and por the under - voltage lockout circuit monitors the voltage of vcc/l do_out pin and the enable input. it assures that the mosfet driver outputs remain in th e off state whenever either of these two signals drop below the set thresholds. normal operation resumes once vcc/ldo _out and enable rise above their thresholds. the por (power on ready) signal is generated when all these signals reach the valid logic level (see system block diagram). when the por is asserted the soft start sequence starts (see soft start section). enable the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under - voltage lockout (uvlo) circuit. therefore, the ir 3898 will turn on only when the voltage at the enable pin exceeds this threshold, typically, 1.2v. if the input to the enable pin is derived from the bus voltage by a suitably programmed resistive div ider, it can be ensured that the ir 3898 does not turn on until the bus voltage reaches the desired level (fig. 4 ). only after the bus voltage reaches or exceeds this level and voltage at the enable pin exceed s its threshold, ir 3898 will be enabled. therefo re, in addition to being a logic input pin to enable the ir 3898 , the enable feature, with its precise threshold, also allows the user to implement an under - voltage lockout for the bus voltage ( pvin ). this is desirable particularly for high output voltage a pplications, where we might want the ir 3898 to be disabled at least until pvin exceeds t he desired output voltage level . pvin (12v) vcc enable intl_ss 10 . 2 v enable threshold = 1 . 2 v figure 4: normal start up, device turns on when the bus voltage reaches 10.2v a resistor divider is used at en pin from pvin to turn on the device at 10.2v. - 18 - august 08, 2012 | data sheet | rev 3.3 18 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 pvin (12v) vcc intl _ ss enable > 1 . 2 v vp > 1 v fig ure 5a: recommended startup for normal operation pvin (12 v) vcc enable > 1 . 2 v intl _ ss vp figure 5 b : reco mmended startup for sequencing operation (ratiometric or simultaneous) pvin (12 v) vcc enable > 1 . 2 v intl _ ss vp vref = 0 figure 5 c : recommended startup for memory tracking operation (vtt - ddr) figure 5 a shows the recommended start - up sequence for the normal (non - tracking, non - sequencing) operation of ir 3898 , when enable is used as logic input. figure 5 b shows the recommended startup sequence for sequenced operation of ir 3898 with enable used as logic input. figure 5 c shows the recommended startup sequence for tracking operation of ir 3898 with enable used as logic input. in normal and sequencing mode op eration, vref is left floating. a 1nf ceramic capacitor is recommended between this pin and gnd. in tracking mode operation, vref should be tied to gnd. it is recommended to apply the enable signal after the vcc voltage has been established. if the enable signal is present before vcc, a 50k? re sistor can be used in series with the enable pin to limit the current flowing into the enable pin. pre - bias startup ir 3898 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 6 a shows a typical pre - bias condition at start up. the sync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. the number of these sta rtup pulses for each step is 16 and its internally programmed. figure 6 b shows the series of 16x8 startup pulses . vo [ v ] [ time ] pre - bias voltage figure 6 a : pre - bias startup ... ... ... hdrv ... ... ... 16 end of pb ldrv 12. 5 % 25% 87. 5% 16 ... ... ... ... f igure 6b: pre - bias startup pulses - 19 - august 08, 2012 | data sheet | rev 3.3 19 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 soft - start ir 3898 has an internal digital soft - start to control the output voltage rise and to limit the current surge at the start - up. to ensure correct start - up, the soft - start sequence initiates when the enable and vcc rise above their uvlo thresholds and generate the p ower on ready (por) signal. the internal soft - start (intl_ss) signal linearly rises with the rate of 0.2mv/s from 0v to 1.5v. figure 7 shows the waveforms during soft start (also refer to fig. 20). the normal vout start - up time is fixed, and is equal to: ( ) 0.65v-0.15v 2.5ms (1) 0.2mv/ s start t = = during the soft start the over - current protection (ocp) and over - voltage protection (ovp) is enabled to protect the device for any short circuit or over voltage condition. por intl _ ss vout 0 . 15v 0 . 65v t 1 t 2 t 3 1 . 5 v 3 . 0 v figure 7: theoretical operation waveforms during soft - start (non tracking / non sequencing) operating frequency the switching frequency can be programmed between 300khz C 1500khz by connecting an external resistor from r t pin to gnd. table 1 tabulates the oscillator frequency versus r t . shutdown ir 3898 can be shut down by pulling the enable pin below its 1.0v threshold. this will tri - state both the hig h side and the low side driver . t able 1 : s witching f requency (f s ) vs . e xternal r esistor ( r t ) rt (k?) freq (khz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 over current protect ion the over current (oc) protection is performed by sensing current through the r ds(on) of the synchronous m osfet . this method enhances the converters efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. the current limit is pre - set internally and is compensated according to the ic temperature. so at different ambient temperature, the over - current trip threshold remains almost constant. over current protection circuit senses the inductor current flowing through the synchronous m osfet closer to the valley point. ocp circuit samples this current for 40nsec typically after the rising edge of the pwm set pulse which has a width of 12.5% of the switching period.the pwm pulse starts at the falling edge of the pwm set pulse. this makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. an oc condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. pgood will go low an d the internal soft start signal will be pulled low. the converter goes into hiccup mode with a 20.48ms (typ.) delay as shown in figure 8. the convertor stays in this mode until the over load or short circuit is removed. the actual dc output current limit point will be greater than the valley point by an amount equal to approximately half of peak to peak inductor ripple current. - 20 - august 08, 2012 | data sheet | rev 3.3 20 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 (2) 2 ocp i i ilimit ? = + i ocp = dc current limit hiccup point i limit = current limit valley point i =inductor ripple current 0 il 0 hdrv current limit 0 ldrv ... ... 0 pgood 20.48ms hiccup figure 8: timing diagram for current limit and hiccup thermal shutdown temperature sensing is provided inside ir 3898 . the trip threshold is typically set to 145 o c. when trip threshold is exceeded, thermal shutdown turns off bot h mosfets and resets the internal soft start. automatic restart is initiated when the sensed temperature drops within the operating range. there is a 20 o c hysteresis in the thermal shutdown threshold. external synchroniza tion ir 3898 incorporates an intern al phase lock loop (pll) circuit which enables synchronization of the internal oscillator to an external clock. this function is important to avoid sub - harmonic oscillations due to beat frequency for embedded systems when multiple point - of- load (pol) regul ators are used. a multi - function pin, rt/sync, is used to connect the external clock. if the external clock is present before the converter turns on, rt/sync pin can be connected to the external clock signal solely and no other resistor is needed. if the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free - running frequency, an external resistor from rt/sync pin to gnd is required to set the free - running frequency. when an external clock is applied to rt/sync pin after the converter runs in steady s tate with its free - running frequency, a transition from the free - running frequency to the external clock frequency will happen. this transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one i s higher. on the contrary, when the external clock signal is removed from rt/sync pin, the switching frequency is also changed to free - running gradually. in order to minimize the impact from these transitions to output voltage, a diode is recommended to ad d between the external clock and rt/sync pin as shown in figure 9a . figure 9 b shows the timing diagram of t hese transitions. ir3898 rt/sync gnd figure 9a : configuration of external synchronization sw sync ... ... gradually change fs1 fs2 fs1 free running frequency synchronize to the external clock return to free- running freq gradually change figure 9 b : timing diagram for synchronization to the external clock (fs1>fs2 or fs1 - 22 - august 08, 2012 | data sheet | rev 3.3 22 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 positive inputs. ideally, the input with the lowest voltage is used for regulating the output voltage and the other two inputs are ignored. in practice the voltage of the other two inputs should be about 200mv greater than the low - voltage input so that their effects can completely be ignored. vp is internally biased to 3.3v via a high impedance path. for normal operation, vp and vref is left floating (vref should have a bypass capacitor). therefore, in normal operating condition, after enable goes high, the internal soft - start (intl_ss) ramps u p the output voltage until vfb (voltage of feedback/fb pin) reaches about 0.5v. then vref takes over and the output voltage is regulated . tracking - mode operation is achieved by connecting vref to gnd. then, while vp=0, enable is taken above its threshold so that the soft - start circuit generates intl_ss signal. after the intl_ss signal reaches the final value (refer to fig. 5 c), ramping up the vp input will ramp up the output voltage. in tracking mode, vfb always follows vp which means vout is always propor tional to vp voltage (typical for ddr/vtt rail applications). the effective vp variation range is 0v~1.2v. in sequencing mode of operation (simultaneous or ratiometric), vref is left floating and vp is kept to ground level until intl_ss signal reaches the final value. then vp is ramped up and vfb follows vp. when vp>0.5v the error - amplifier switches to vref and the output voltage is regulated with vref.the final vp voltage after seq uencing startup should between 0.7 v ~ 3.3v. boot vcc/ldo fb comp gnd pgnd sw vo1 (master) pgood pgood rt/ sync 6.8 v < vin < 16 v pvin vp s_ctrl vin vref en r a r b vsns boot vcc/ldo fb comp gnd pgnd sw vo2 (salve) pgood pgood rt/ sync pvin vp vo1 (master) s_ctrl vin vref en r e r f r c r d 6. 8 v < vin < 16 v vsns figure 12: appli cation circuit for simultaneous and ratiometric sequencing tracking and sequencing operations can be implemented to be simultaneous or ratiometric (ref er to fig. 13 and 14). figure 12 shows typical circuit configuration for sequencing operation. with this power - up configuration, the voltage at the vp pin of the slave reaches 0.5v before the fb pin of the master. if r e /r f =r c /r d , simultaneous startup is achieved. that is, the output vol tage of the slave follows that of the master until the voltage at the vp pin of the slave reaches 0.5 v. after the voltage at the vp pin of the slave exceeds 0.5v, the internal 0.5v reference of the slave dictates its output voltage. in reality the regula tion gradually shifts from vp to internal vref. the circuit shown in fig. 12 can also be used for simultaneous or ratiometric tracking operation if vref of the slave is connected to gnd. table 2 summarizes the required condi tions to achieve simultaneous/ ra tiometric tracking or sequencing operations. vcc vref = 0 . 5 v 1 . 2 v soft start ( slave ) enable ( slave ) vo 1 ( master ) vo 2 ( slave ) (a ) vo 1 ( master ) vo 2 ( slave ) (b ) figure 13: typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric - 23 - august 08, 2012 | data sheet | rev 3.3 23 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 vcc vref = 0 v ( slave ) 1 . 2 v soft start ( slave ) enable ( slave ) vo 1 ( master ) vo 2 ( slave ) (a ) vo 1 ( master ) vo 2 ( slave ) (b ) figure 14: typical waveforms in tracking mode of operat ion: (a) simultaneous, (b) ratiometric t able 2: r equi red c onditions for s imultaneous / r atiometric t racking and s equencing (f ig . 12) operating mode vref (slave) vp required condition normal (non - sequencing, non - tracking) 0.5v (floating) floating D simultaneous sequencing 0.5v ramp up from 0v r a /r b >r e / r f =r c /r d ratiometric sequencing 0.5v ramp up from 0v r a /r b >r e / r f > r c /r d simultaneous tracking 0v ramp up from 0v r e /r f =r c /r d ratiometric tracking 0v ramp up from 0v r e /r f > r c /r d vref this pin reflects the internal reference voltage which is used by the error amplifier to set the output voltage. in most operating conditions this pin is only connected to an external bypass capacitor and it is left floating. a 1nf ceramic capacitor is rec ommended for the bypass capacitor . to keep stand by current to minimum, vref is not allowed to come up until en starts going high. in tracking mode this pin should be pulled to gnd. for margining applications, an external voltage source is connected to vref pin and overrides the internal reference voltage. the external voltage source should have a low internal resistance (<100 ) and be able to source and sink more than 25a . power good output (t racking, sequencing, vref mar gining) ir3898 continually monitors the output voltage via the sense pin (vsns) voltage. the vsns voltage is an input to the window comparator with upper and lower threshold of 0.6v and 0.45v respectively. pgood signal is high whenever vsns voltage is within the pgood comparator wi ndow thresholds. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. the threshold is set differently at different operating modes and the results of the comparison sets the pgood signa l. figures 15 , 1 6 , and 17 show the timing diagram of the pgood signal at different operating modes. vsns signal is also used by ovp comparator for detecting output over voltage condition. 0 0 0 vref pgood vsns 0 . 5 v 1 . 2 * vref 0 . 85 * vp 1 . 28 ms 1 . 28 ms ovp latch 0 . 9 * vp figure 15: non - sequence, non - tracking s tartup and vref margin (vp pin floating) 0 . 3 v 0 0 0 vp vsns 0 . 4 v pgood 0 . 9 * vp 1 . 2 * vp 1 . 28 ms figure 16: vp tracking (vref =0v) - 24 - august 08, 2012 | data sheet | rev 3.3 24 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 internal ss 0 0 0 0 vref pgood vsns (0.7v - 26 - august 08, 2012 | data sheet | rev 3.3 26 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 design example the following example is a typical application for ir 3898 . the application circuit is shown in fig.28. = =12 v ( 10%) =1 2 v = 6 a ripple voltage= 1% * 5% * 50% =600 khz in o o o oo s v v. i v v v load transient f ( for ) enabling the ir 3898 as explained earlier, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage as shown in fig. 22. ir3898 enable vin r1 r2 figure 22: using enable pin for uvlo implementation for a typical enable threshold of v en = 1. 2 v 2 (min) 12 * 1.2 (7) in en r vv rr = = + 21 min (8) en in( ) en v rr vv = ? for v in (min) =9.2v, r 1 =49.9k and r 2 =7.5k ohm is a good choice. programming the frequency for f s = 600 khz, select r t = 39.2 k o , using table 1. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of t he error amplifier, which is internally referenced to 0.5v. the divider ratio is set to provide 0.5v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: 5 6 1 (9) o ref r vv r ?? = ? + ?? ?? when an external resistor divider is connected to the output as shown in fig. 23. 65 (10) ref o ref v rr vv ?? = ? ?? ?? ? ?? for the calculated values of r5 and r6 , see feedback compensation section. ir3898 fb vout r5 r6 figure 23: typical application of the ir3898 for programming the output voltage bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected t o the source of the control fet . this is achieved by us ing a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c1). the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled down to ground. t he capacitor charges towards v cc through the internal bootstrap diode (fig.24), which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c1 is approximately given as : (11) c cc d vv v ? ? - 27 - august 08, 2012 | data sheet | rev 3.3 27 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 when the control fet turns on in the next cycle, the capacitor node connected to sw rises to the bus voltage v in . however, if the value of c1 is appropriately chosen, the voltage v c across c1 remains approximately unchanged and the voltage at the boot pin becomes: (12) boot in cc d v vvv ? + ? l ir3898 vc c 1 v in v cc sw + - boot pgnd + v d - cvin figure 24: bootstrap circuit to generate vc voltage a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple current generated during th e on time of the control fet should be provided by the input capacitor. the rms value of this ripple is expressed by: (1 ) (13) rms o i id d = ? ? ? (14) o in v d v = where: d is the duty cycle i rms is the rms value of the input capacitor current. io is the output current. for i o = 6a and d = 0.1, the i rms = 1.8 a. ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is advisable to have 3x10uf, 25 v ceramic capacitors, c3216x5r1 e 106m from tdk. in addition to these, although not mandatory, a 1x330uf, 25v smd capacitor eev - fk1e331p from panasonic may also be used as a bulk capacitor and is recommended if the input power su pply is not located close to the converter. inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. a low inductor value causes large ripple current, resulting in the smaller size, faster respons e to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( i ). the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: ( ) 1 ; (15) * in o s o in o in s i v v l td tf v lvv v if ? ? = ? ?= ? ? = ?? ?? where : v in = maximum input voltage v 0 = output voltage i = inductor peak - to- peak ripple current f s = switching frequency t = o n time d = duty cycle if i c 3 0%* i o , then the output inductor is calculated to be 1.0 h. select l = 1.0 h, spm6550t - 1r0m , from tdk which provides a compact, low profile inductor suitable for this application. - 28 - august 08, 2012 | data sheet | rev 3.3 28 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 output capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criteria is normally based on the value of the effective series resistance (esr). however the actual capacitance value and the e quivalent series inductance (esl) are other contributing components. these components can be described as : ()()() () () () * * (16) 8* * o o esr o esl o c o esr l in o o esl l oc os vv v v v i esr vv v esl l i v cf ? =? +? +? ?=? ? ?? ?= ?? ?? ? ?= where : v 0 = output voltage ripple i l = inductor ripple current since the output capacitor has a major role i n the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the ir 3898 can perform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size . therefore it is advisable to select ceramic capacitors due to their low esr and esl and small size. four of tdk c2012x5r0j226m (22uf/0805/ x5r/ 6.3v) capacitors is a good choice. it is also recommended to use a 0.1f ceramic capacitor at the output for high frequency filtering. feedback compensation the ir 3898 is a voltage mode controller. the control loop is a single voltage feedback path including an error amplifier and a comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to close the control loop at hi gh cross over frequency with phase margin greater than 45 o . the output lc filte r introduces a double pole, - 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o . the resonant frequency of the lc filter is expressed as fo llows: 1 (17) 2 lc oo f lc = ?? figure 2 5 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alon e, the system runs the risk of being unstable. phase 0 0 f lc 0 frequency f lc frequency 0 0 - 180 0 0 db - 40db / decade - 90 gain figure 25: gain and phase of lc filter the ir 3898 uses a voltage - type error amplifier with high - gain (110db) and high - bandwidth (30mhz). the output of the amplifier is available for dc gain control and ac phase compensation. the error amplifier can be compensated ei ther in type ii or type iii compensation. type ii compensation is shown in fig. 26. this method requires that the output capacitor s have enough esr to satisfy stability requirements. if the output capacitors esr generates a zero at 5khz to 50khz, the zero generates acceptable phase margin and the type ii compensator can be used. - 29 - august 08, 2012 | data sheet | rev 3.3 29 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 the esr zero of the output capacitor is expressed as follows: 1 (18) 2 esr o f * esr* c = v out v ref r 6 r 5 c pole c 3 r 3 ve f z f pole e / a z f frequency gain ( db ) h ( s ) db fb comp z in figure 26: type ii compensation network and its asymptotic g ain plot the transfer function ( v e /v out ) is given by: 33 53 1 ( ) (19) f e out in z v sr c hs v z sr c + = = ? = ? the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: ( ) 3 5 33 (20) 1 (21) 2* * z r hs r f rc = = first select the desired zero - crossover frequency ( f o ): ( ) o (22) and f 1/5~1/10 * o esr s ff f > use the following equation to calculate r3: 5 3 2 ** * (23) * osc o esr in lc v ff r r vf = where: v in = maximum input voltage v osc = amplitude of the oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: 75 % * 1 0.75* (24) 2* z lc z oo ff f lc = = use equations (20), (21) and (22) to calculate c3. one more capacitor is sometimes added in parallel with c3 and r3. this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: 3 3 3 1 (25) * 2* * p pole pole f cc r cc = + the pole sets to one half of the switching frequency which results in the capacitor c pole : 3 3 3 11 (26) 1 pole s s c *r *f *r *f c = ? ? for a general solution for unconditional stability for any type of output capacitors, and a wide range of esr values , a type iii compensation netw ork can be used , as shown in fig. 27 . - 30 - august 08, 2012 | data sheet | rev 3.3 30 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 v out v ref r 6 r5 r 4 c 4 c2 c3 r 3 ve f z 1 f z 2 f p 2 f p 3 e / a z f z in frequency gain ( db ) | h(s) | db fb comp figure 27: type iii compensation network and its asymptotic gain plot again, the transfer function is given by: in f out e z z s h v v ? = = ) ( by replacing z in and z f , according to fig. 27, the transfer function can be expressed as: ( ) 33 4 4 5 23 5 2 3 3 44 23 (1 ) 1 * () ( ) 1 (1 ) (27) sr c sc r r cc hs sr c c sr sr c cc + ++ ?? ?? ? ?? ?? = ++ + ?? ?? + ?? ?? the compensation network has three poles and two zeros and they are expressed as follows: 1 2 44 3 32 23 3 23 0 (28) 1 (29) 2* * 11 (30) 2* * * 2* p p p f f rc f rc cc r cc = = = ? ?? ?? + ?? 1 33 2 4 4 5 45 1 (31) 2* * 11 (32) 2* *( ) 2* * z z f rc f c r r cr = = ? + cross over frequency is expressed as: 34 1 * * * (33) 2* * in o osc o o v f rc v lc = based on the frequency of the zero generated by the output capacitor and its esr, relative to crossover frequency, the compensation type can be different. table 3 shows the compensation types for relative locations of the crossove r frequency. t able 3: d ifferent types of co mpensators compensator type f esr vs f o typical output capacitor type ii f lc < f esr < f o < f s /2 electrolytic type iii f lc < f o < f esr sp cap, ceramic the higher the crossover frequency is, the potentially faster the load transient response will be. however, the crossover frequency should be low enough to attenuate the switching noise. typically, the contr ol loop bandwidth or crossover frequency ( f o ) is selected such that: ( ) s o f f * 1/10 ~ 1/5 the dc gain should be large enough to provide high dc - regulation accuracy. the phase margin should be greater than 45 o for overall stability. for this design we have: v in =12v v o =1.2v v osc =1. 8 v (this is a function of vin, see feed forward section) v ref =0.5v l o = 1.0 uh c o = 4 x22uf, esr 3 m each it must be noted here that the value of the capacitance used in the compensator design must be the small signal value. for instance, the small signal capacitance of the 22uf capacitor used in this design is 10uf at 1.2 v dc bias and 600 khz frequency. it is this value that must be used for all computations related to the compensation. the small signal - 31 - august 08, 2012 | data sheet | rev 3.3 31 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 value may be obtained from the manufacturers datasheets, design tool s or spice models. alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency f lc and using equation (1 7 ) to compute the small signal c o . these result in : f lc =2 5.2 khz f esr =5.3 mhz f s /2 =300 khz select crossover frequency f 0 =1 2 0 khz since f lc - 33 - august 08, 2012 | data sheet | rev 3.3 33 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 boot vcc/ldo_out fb comp gnd pgnd sw s_ctrl vo=1.2v pgood enable rt/sync vin = 12 v vin vp r 5 3.32k 2.37k co = 4 x 22 uf lo 1 uh c4 2 . 2 nf r4 64.9 r 3 1k c3 33nf c2 390pf c 1 0 . 1 uf c in = 3 x 10uf r t 39.2 . k r pg 49.9k r1 49.9 k r2 7.5k ir 3898 2.2 uf c vcc pvin vref 100pf cref vsns r6 r7 3.32k 2.37k r8 u1 c5 0.1uf c6 0.1uf external vcc=5v figure 28b : application circuit for a 12v to 1.2v, 6a point of load converter using external 5v vcc - 34 - august 08, 2012 | data sheet | rev 3.3 34 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 boot vcc/ldo_out fb comp gnd pgnd sw s_ctrl vo=1v pgood enable rt/sync vin = 5 v vin vp r 5 3.32k 3.32k co = 4 x 22 uf lo 0.68 uh c4 2 . 2 nf r4 100 r 3 2.0k c3 10nf c2 220pf c 1 0 . 1 uf c in = 4 x 10uf r t 39.2 . k r pg 49.9k ir 3898 2.2uf c vcc pvin vref 100pf cref vsns r6 r7 3.32k 3.32k r8 u1 c5 0.1uf c6 0.1uf pgood enable figure 29 : application circuit for a 5v to 1v, 6a point of load converter suggested bill of materials for the application circuit 5v to 1v part reference qty value description manufacturer part number cin 3 10uf 1206, 16v, x5r, 20% tdk c3216x5r1e106m c1 c5 c6 3 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01b cref 1 1nf 0603,50v,x7r murata grm188r71h102ka01b c4 1 2200pf 0603,50v,x7r, 10% murata grm188r71h222ka01b c2 1 220pf 0603,50v,x7r, 10% murata grm188r71h221ka01d co 4 22uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j226m cvcc 1 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m c3 1 10nf 0603, 25v, x7r, 10% murata grm188r71e103ka01j lo 1 0.68uh smd 7.05x6.6x4.8 mm, 3.9m cyntec pcmb065t - r68ms r3 1 2.0k thick film, 0603,1/10w,1% panasonic erj - 3ekf2001v r5 r6 r7 r8 4 3.32k thick film, 0603,1/10w,1% panasonic erj - 3ekf3321v r4 1 100 thick film, 0603,1/10w,1% panasonic erj - 3ekf1000v rt 1 39.2k thick film, 0603,1/10w,1% panasonic erj - 3ekf3922v rpg 1 49.9k thick film, 0603,1/10w,1% panasonic erj - 3ekf4992v u1 1 ir3898 pqfn 4x5mm ir ir3898mpbf - 35 - august 08, 2012 | data sheet | rev 3.3 35 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 vo=0.6v boot vcc/ldo_out fb comp gnd pgnd sw s_ctrl pgood pgood enable rt/sync vin = 12 v vin vp r 5 6.65k co = 6 x 22 uf lo 680nh c4 2 . 2 nf r4 215 r 3 2k c3 15nf c2 270pf c 1 0 . 1 uf c in = 3 x 10 uf r t 39.2 k r pg 49.9k r1 49.9k r2 7.5k ir 3898 2.2uf c vcc pvin vref vsns r7 6.65k cvin 1.0uf u1 c5 0.1uf c6 0.1uf 1.5k 1.5k r6 vddq = 1.2 v r8 10nf c7 n/s (optional) figure 30 : application circuit for a 12v input, 0. 6 v output, vtt rail boot vcc/ldo_out fb comp gnd pgnd sw s_ctrl vo=0.6v pgood pgood enable rt/sync vin=1.2v vin vp r 5 4.99k co = 6 x 22 uf lo 0.35uh c4 2.2nf r4 158 r 3 5.76k c3 3.9nf c2 91pf c 1 0 . 1 uf c in = 3 x 22 uf r t 39.2 k r pg 49.9k ir 3898 2.2uf c vcc pvin vref vsns r7 4.99k u1 c5 0.1uf c6 0.1uf 1.5k 1.5k r6 r8 10nf c7 ext vcc enable vin=1.2v n/s (optional) figure 3 1 : application circuit for a 1.2 v input, 0. 6 v output, vtt rail - 36 - august 08, 2012 | data sheet | rev 3.3 36 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 typical operating wa veforms vin = 12 v, vo = 1. 2 v, io ut = 0 - 6a room temperature, no a ir f low figure 32 : start up at 6a load , figure 3 3 : start up at 6a load, ch 1 :v in , ch 2 :v o , ch 3 : pgood , ch 4 : enable ch 1 :v in , ch 2 :v o , ch 3 :vcc, ch 4 :p good figure 3 4 : start up with 1v pre bias figure 3 5: output voltage ripple 0a load ch2 :v o 6a load ch2 :v o figure 3 6: inductor node at 6a load , ch3:lx figure 3 7: short circuit recovery ch2:vout,ch4:iout(2a/div) - 37 - august 08, 2012 | data sheet | rev 3.3 37 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 typical operating wa veforms vin = 12 v, vo = 1. 2 v, io ut = 0 - 6a room temperature, no a ir f low figure 3 8: turn on at no load showing vcc level figure 3 9: turn on at full load showing vcc level ch 1 :v in , ch 2 :v o , ch 3 :vcc, ch 4 : inductor current ch 1 :v in , ch 2 :v o , ch 3 :vcc, ch 4 : inductor current figure 40: transient response, 3 to 6a step at 2.5a/usec slew rate ch 2 :v o , ch 4 : iout(2a/div) - 38 - august 08, 2012 | data sheet | rev 3.3 38 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 typical operating wa veforms vin = 12 v, vo = 1. 2 v, io ut = 0 - 6a room temperature, no a ir f low figure 41 : bode plot at 6 a load shows a bandwidth of 110.8 khz and phase margin of 50.6 degrees figure 42 : thermal image of the b oard at 6a l oad , test p oint 1 is ir389 8, test p oint 2 is inductor - 39 - august 08, 2012 | data sheet | rev 3.3 39 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 typical operating wa veforms vin = 12 v, vo = 1. 2 v, io ut = 0 - 6a room temperature, no a ir f low figure 4 3: feed forward for vin change from 7 - 16- 7v figure 4 4: start/stop using s - ctrl pin ch2 - vo,ch 4 : vi n ch1 - pgood,ch2:vout;ch3 - en.ch4 - s- ctrl figure 4 5: external frequency synchronization to figure 4 6: over voltage protection 800khz from free running 600khz, c h 2 :v o , ch 3 : lx , ch 4 : rt/sync voltage ch2 - vo,ch43 - pgood figure 4 7: voltage margining using vref pin figure 4 8: voltage tracking using vp pin ch 2 :v o , ch 3 : pgood , ch 4 : vref ch 1 :v o , ch 3 : pgood , ch 4 : vp - 40 - august 08, 2012 | data sheet | rev 3.3 40 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 layout recommendatio ns the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make the connections for the power components in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for powe r distribution and heat dissipation. the inductor, output capacitors and the ir 3898 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input cap acitor directly at the pvin pin of ir 3898 . the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass components such as capacitors for vin, vcc and vref should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all sig nals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. it is reco mmended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 4 - layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. figure s 46a - d illustrates the implementation of the layou t guidelines outlined above, on the irdc3898 4 - layer demo board . figure 4 9 a: irdc 3898 d emo board l ayout c onsiderations C top layer compensation parts should be placed as close as possible to the comp pin resistor rt and vref decoupling cap should be placed as close as possible to their pins enough copper & minimum ground length path between input and output all bypass caps should be placed as close as possible to their connecting pins sw node copper is kept only at the top layer to minimize the switching noise - 41 - august 08, 2012 | data sheet | rev 3.3 41 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 figure 4 9b : irdc 3898 d emo board l ayout c onsiderations C bottom layer analog ground plane power ground plane figure 4 9 c: irdc3898 demo board l ayout c onsiderations C mid layer 1 figure 4 9 d: irdc 3898 d emo board l ayout c onsiderations C mid layer 2 single point connection between agnd & pgnd, should be close to the supirbuck kept away from noise sources feedback and vsns trace routing should be kept away from noise sources - 42 - august 08, 2012 | data sheet | rev 3.3 42 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 pcb metal and component placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self - centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self - centering on specific processes. for further information, please refer to supirbuck? multi - chip module (mcm) power quad flat no - lead (pqfn) board mounting application n ote . (an1132) figure 50: pcb metal pad spacing (all dimensions in mm) * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format - 43 - august 08, 2012 | data sheet | rev 3.3 43 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 solder resist ? ir recommends that the larger power or land area pads are solder mask defined (smd.) this allows the underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. ? when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in x & y.) ? however, for the smaller signal type leads around the edge of the device, ir recommends that these are non solder mask defined or copper defined. ? when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x&y,) in order to accommodate any la yer to layer misalignment. ? ensure that the solder resist in - between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. figure 51: solder resist * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format - 44 - august 08, 2012 | data sheet | rev 3.3 44 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 stencil design ? stencils for pqfn can be used with thicknesses of 0.100 - 0.250mm (0.004 - 0.010"). stencils thinner than 0.100mm are unsuitabl e because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm - 0.200mm (0.005 - 0.008"), with suitable reductions, give the best results. ? evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. this design is for a stencil thickness of 0.127mm (0.005"). the reduction should be adjusted for stencils of other thicknesses. figure 52: stencil pad spacing (all dimensions in mm) * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format - 45 - august 08, 2012 | data sheet | rev 3.3 45 ir3898 6a highly integrated supirbuck tm single - input voltage, synchronous buck regulator pd - 9766 2 marking information package information ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 this product has been designed and qualified for the industrial market visit us at www.irf.com for sales contact information data and specifications subject to change without notice 12/11. figure 54: package dimensions figure 53: marking information |
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